Joseph Bulone

CTO at KPInsight Analytics
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Contact Information
us****@****om
(386) 825-5501
Location
Greater Lyon Area, FR

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Bio

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Experience

    • Technology, Information and Internet
    • 1 - 100 Employee
    • CTO
      • Sep 2016 - Present

      - Data Analytics tools (Google Analytics, Google Tag Manager, Commander Act, ...) - In-house tool developments (PHP, javascript, ...) - ... - Data Analytics tools (Google Analytics, Google Tag Manager, Commander Act, ...) - In-house tool developments (PHP, javascript, ...) - ...

    • France
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Cofounder, Head of Unit Systems Integration, Design verification expert
      • Nov 2008 - Aug 2014

      - Simulation / debug (VHDL, VERILOG, SV, OVM) - Hardware emulation - Formal property checking (PSL, SVA) - Clock Domain Crossing checking - Verification framework development for automation and continuous integration - Investigation, development and integration of formal tools as theorem provers (acl2) or proof assistants (isabelle) - Cryptographic algorithm benchmarking / optimization - Chip modeling at SystemC level (coarse grain) + visualization tool writing for simulation results Show less

    • Switzerland
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Advanced design flow expert
      • Jan 2008 - Oct 2008

      - Training : « from creativity to innovation »- Setup and follow-up of funded projects- Patent selection- Guiding R&D and hardware emulation / fast prototyping machine investments

    • Hardware emulation team manager
      • Jan 2005 - Dec 2007

      - Central service team involved in all main ST digital products- Interface with the EDA vendors for the hardware emulation / fast prototyping machines- Advanced developments and services in: * Transactional hardware co-emulation platforms for design flow efficiency improvement * Hardware emulation for power estimation * Hardware emulation for radiation robustness computation

    • Engineer/Researcher
      • Oct 1989 - Dec 2004

      - Design For testability- Hardware emulation, co-emulation- ATM chip(s): design and verification- Video Codec chip(s): verification and embedded software

Education

  • Grenoble INP - UGA
    PhD, Microelectronics
    1990 - 1994
  • Université Joseph Fourier (Grenoble I)
    master, Microelectronics
    1989 - 1990
  • Ecole polytechnique
    engineer
    1986 - 1989

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