Experience

Cerebras Systems

• United States
• Computer Hardware
• 200 - 300 Employee

• Member Of Technical Staff

  • Dec 2018 - Present

  LLM training stack optimization. Develop and optimize recompute/ reverse checkpoint algorithm for LLM training Develop and optimize activation offload algorithm Develop training memory profiling tool Develop and optimize buffer allocation algorithm for LLM pipeline training LLM training stack optimization. Develop and optimize recompute/ reverse checkpoint algorithm for LLM training Develop and optimize activation offload algorithm Develop training memory profiling tool Develop and optimize buffer allocation algorithm for LLM pipeline training



Synopsys Inc

• United States
• Software Development
• 700 & Above Employee

• Sr R&D Engineer

  • Mar 2016 - Nov 2018

  Develop system level routing algorithm for FPGA-based emulation system Develop partitioning tool to assist compilation on multi-die FPGA Architecture exploration on new hardware with varies connectivity topology Develop system level routing algorithm for FPGA-based emulation system Develop partitioning tool to assist compilation on multi-die FPGA Architecture exploration on new hardware with varies connectivity topology



UCLA

• United States
• Higher Education
• 700 & Above Employee

• Ph.D in Electrical and Computer Engineering

  • Sep 2013 - Mar 2018

• Teaching Assistant

  • Sep 2013 - Feb 2016

  Lead discussion



Synopsys Inc

• United States
• Software Development
• 700 & Above Employee

• Software Engineer Internship

  • Jul 2015 - Sep 2015

  Developed routing engine for world fastest emulator Optimized STA timer Developed routing engine for world fastest emulator Optimized STA timer



USC Information Sciences Institute

• United States
• Research
• 200 - 300 Employee

• Visiting Research Assistant

  • Jun 2014 - Aug 2014

  FPGA Trustworthy Verification FPGA Trustworthy Verification



USC Information Sciences Institute

• United States
• Research
• 200 - 300 Employee

• Visiting research assistant

  • Jun 2013 - Aug 2013

  Develop and implement a fault injection infrastructure for FPGA IP core functionality and reliability evaluation. Hardware/Software co-design to evaluate the results of the experiments. Develop and implement a fault injection infrastructure for FPGA IP core functionality and reliability evaluation. Hardware/Software co-design to evaluate the results of the experiments.



MTU Maintenance

• Germany
• Aviation and Aerospace Component Manufacturing
• 700 & Above Employee

• Mechanical Engineering Intern

  • Jun 2010 - Aug 2010