Experience

New Wave Design and Verification

• United States
• Defense and Space Manufacturing
• 1 - 100 Employee

• Vice President Of Business Development

  • Dec 2018 - Present

  Greater Minneapolis-St. Paul Area

• Director Of Business Development

  • Dec 2016 - Dec 2018

  Greater Minneapolis-St. Paul Area - Responsible for all new business development activities at New Wave DV. - Drive senior level customer engagement from initial conversation through sales closing. - Manage regional sales managers, sales representatives, inside sales, and marketing teams. - Provide strategic vision to engineering and management teams for product direction.

• Senior Business Development Manager

  • Jan 2013 - Dec 2016

  Greater Minneapolis-St. Paul Area • Lead new business development including: market research, customer introductions, customer meetings, provide technical briefings, and lead proposal writer. • Performed multiple chip architecture efforts, used as technical content for new business proposals. Present to customer via written proposals, white papers, and on-site presentations. •Responsible for project planning, schedule and budget approval, and project technical scope.



Lockheed Martin

• United States
• Defense and Space Manufacturing
• 700 & Above Employee

• Electrical Engineer Sr.

  • Jul 2009 - Jan 2013

  Greater Minneapolis-St. Paul Area •Completed several large scale Altera Stratix5 FPGA design projects using Verilog/VHDL for design, SystemVerilog (OVM) for verification, and the Mentor QuestaSim tool suite for simulation. •Part of multiple chip architecting, design, and verification efforts. Designed PCIe controller, 10G Ethernet interface, register sets, bus interfaces, Event/Interrupt controller, DMA controllers, and traffic arbiters. •Designed and wrote SystemVerilog OVM verification environment including reference… Show more •Completed several large scale Altera Stratix5 FPGA design projects using Verilog/VHDL for design, SystemVerilog (OVM) for verification, and the Mentor QuestaSim tool suite for simulation. •Part of multiple chip architecting, design, and verification efforts. Designed PCIe controller, 10G Ethernet interface, register sets, bus interfaces, Event/Interrupt controller, DMA controllers, and traffic arbiters. •Designed and wrote SystemVerilog OVM verification environment including reference models, drivers, monitors, stimulus generators, sequences, agents, and scoreboards. Used for generating constrained random tests in a full chip simulation environment. •Completed top level FPGA integration. Defined pinout, third party IP, and integrated developed IP. Handled all top level signal interconnect. •Principal author of the Interface Control Document for the chip. Responsible for organization of document, high level descriptions, diagrams, and tables. •Performed conceptual designs and trade studies for new business opportunities, input was part of the technical proposal.

• Engineering Leadership Development Program

  • Jun 2006 - Jun 2009

  Greater Minneapolis-St. Paul Area •Completed the Lockheed Martin Engineering Leadership Development Program in December 2009. Three year program consisting of a technical master’s degree, challenging work assignments in various programs (below), leadership training, mentoring, and volunteering. Digital Design, Simulation & Verification (1/08-6/09) •Performed functional verification, and formal testing of several special purpose Fibre Channel Network Interface FPGAs. Designs done in VHDL, verification done in… Show more •Completed the Lockheed Martin Engineering Leadership Development Program in December 2009. Three year program consisting of a technical master’s degree, challenging work assignments in various programs (below), leadership training, mentoring, and volunteering. Digital Design, Simulation & Verification (1/08-6/09) •Performed functional verification, and formal testing of several special purpose Fibre Channel Network Interface FPGAs. Designs done in VHDL, verification done in SystemVerilog using OVM architecture. •Designed and wrote verification architecture components including reference models, drivers, monitors, stimulus generators, and scoreboards. •Spent five months at L3 in New Jersey working hardware integration, board bring up, and software drivers with the customer. Responsible for working independently to resolve issues and represent Lockheed Martin. R&D Programs Analyst (2/07 – 1/08) •Worked directly for the R&D director managing day to day project plans and execution. Also responsible for long range planning input based on technology and business opportunities. •Responsible for determining and reporting current spend plans, technical challenges, project changes, customer relationships, and staffing needs to executive management team. Hardware Design/Integration (6/06 – 6/07) •R&D project to integrate a Systolic Processing Array system at Lockheed Martin Eagan. System consists of 1,000 16-bit processors implemented in FPGAs operating in parallel. •Wrote VHDL hardware design for different imagers and fiber optic gyros. •Wrote and modified software in C++ for varying applications. •Gave demonstrations and explanations of the system to various engineers, business development representatives, and business leaders.



CyberOptics

• United States
• Appliances, Electrical, and Electronics Manufacturing
• 100 - 200 Employee

• Electrical Engineering Intern

  • Jan 2005 - May 2006