Experience

3Red Partners

• United States
• Financial Services
• 1 - 100 Employee

• FPGA Engineer

  • Oct 2020 - Present



Akuna Capital

• United States
• Capital Markets
• 400 - 500 Employee

• Garden Leave

  • Jun 2020 - Oct 2020

• Senior FPGA Developer

  • Jan 2018 - Jun 2020

  Senior FPGA Engineer working on low-latency / high-performance trading system

• FPGA Engineer

  • Jun 2016 - Jan 2018

  FPGA Engineer working on low-latency / high-performance trading system



Analog Devices

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Mixed Signal Verification / Signal Integrity Engineer

  • Jan 2012 - Jun 2016

  Mixed Signal Verification - SV + SPICE + UVM + Coverage/Metric driven verification for AMS (lots more acronyms than I care to admit). Basically, I verify circuits and stuff. Was a Digital Designer before so I can easy work with / bridge the gap b/w Analog and Digital Designer. Signal Integrity - Laminate Design / 2.5D EM package simulation / IBIS-AMI. Basically if it is signal integrity and it is related to SERDES and channel simulation, I probably work on it. Mixed Signal Verification - SV + SPICE + UVM + Coverage/Metric driven verification for AMS (lots more acronyms than I care to admit). Basically, I verify circuits and stuff. Was a Digital Designer before so I can easy work with / bridge the gap b/w Analog and Digital Designer. Signal Integrity - Laminate Design / 2.5D EM package simulation / IBIS-AMI. Basically if it is signal integrity and it is related to SERDES and channel simulation, I probably work on it.



Immedia Semiconductor

• United States
• Computer Hardware Manufacturing
• 1 - 100 Employee

• ASIC Engineer

  • Mar 2010 - Jan 2012

  FPGA/Frontend Digital Designer working on Custom Video Encoding Datapath FPGA/Frontend Digital Designer working on Custom Video Encoding Datapath



Analog Devices

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Digital Design Engineer

  • Jul 2008 - Mar 2010

  Custom Digital ASIC designer in HSI (high speed interconnect). Everything from Synthesis, to Verification, to Place and Route, and Timing Closure. Custom Digital ASIC designer in HSI (high speed interconnect). Everything from Synthesis, to Verification, to Place and Route, and Timing Closure.



AMD

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• ASIC PD Intern

  • May 2007 - Aug 2007

  ASIC PD Engineer under Victor Ma. Some OpenAccess work. Some TB work. Some CAD (script) work that glue EDA tools together. ASIC PD Engineer under Victor Ma. Some OpenAccess work. Some TB work. Some CAD (script) work that glue EDA tools together.



NVIDIA

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• Hardware Intern

  • May 2006 - Aug 2006

  Qual Engineer for the GeForce Go 7600. Characterized signal integrity for LVDS/TMDS/PCI-E/Critical Delay Path. Modify a thermal stress board for GPU. Qual Engineer for the GeForce Go 7600. Characterized signal integrity for LVDS/TMDS/PCI-E/Critical Delay Path. Modify a thermal stress board for GPU.



Elitegen

• Software Dev

  • 2003 - 2004

  MySQL DBA. Some PHP web work. Linux Server Administrator. MySQL DBA. Some PHP web work. Linux Server Administrator.