Experience

Nanya Technology

• Taiwan
• Semiconductors
• 300 - 400 Employee

• Staff Design Engineer

  • Aug 2022 - Present

• Senior Engineer

  • Jun 2017 - Sep 2022



Oracle

• United States
• IT Services and IT Consulting
• 700 & Above Employee

• Principal Design Engineer

  • Jan 2014 - May 2017

  Custom Circuit Design implementation from RTL to GDS including design of schematic, semi-custom layout, functional verification, margin verification, timing closure & back-end analysis such as ERC, EM for signals and power line, IR drop, noise analysis, and sign-off for High Speed, Low Power SRAM, cache blocks - l3d tag design (5.0GHz, 20nm CMOS) - l3d csa design (5.5GHz, 10nm FinFET) - array size optimization for l3d tag and l3d csa - size optimization of rcs, wcs, and blrec for 10nm FinFET and calculation of throughput and latency for HC/HD SRAM - schematic entry for cell array, x-decoder, io slice, redundancy, DFT-aware top block and RTL update - clock tuning, power simulation, and power model generation - layout supervision and modification of array, block layout using in-house P&R tool, physical verification, extraction and timing closure - Back-end flow running (ERC, EM for signals and power line, IR drop, noise analysis) and sign off Show less



Micron Technology

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Design Engineer

  • Aug 2010 - Sep 2013

  - Timing, function and current simulation, layout supervision and failure analysis - Full chip signal hookup and simulation of WideIO1 4Gb (30nm process) - Full chip ERC and signal EM check of WideIO1 4Gb and LPDDR4 8Gb (30nm process) - Level shifters, self-refresh block, phase splitters, test mode circuit block entry and simulation used in LPDDR4 - Verilog simulation with Liberty model for LPDDR3 design - Timing, function and current simulation, layout supervision and failure analysis - Full chip signal hookup and simulation of WideIO1 4Gb (30nm process) - Full chip ERC and signal EM check of WideIO1 4Gb and LPDDR4 8Gb (30nm process) - Level shifters, self-refresh block, phase splitters, test mode circuit block entry and simulation used in LPDDR4 - Verilog simulation with Liberty model for LPDDR3 design



ZMOS Technology, Inc.

• Semiconductor Manufacturing
• 1 - 100 Employee

• Senior Design Engineer

  • Oct 2007 - May 2010

  - Timing, function and power simulation, layout supervision and failure analysis - Leakage and standby current simulation and analysis of each unit level and full chip level - Sneak current path detection in alternating power gate - Signal ordering, shielding, width and space sizing of critical signals and correspondent pre-routing to avoid unexpected cross-talk - Timing, function simulation, power network modeling/simulation of 256Mb, 512Mb LPSDR/LPDDR1 SDRAM (72nm, 1.8V/2.5V, 200MHz) and 128Mb LPSDR SDRAM (99nm, 1.8V/2.5V, 166MHz) - Design and modeling of SRAM macro (512X24, 0.16um, Tprop=2ns, 100MHz, 1.8V) - Behavior verilog model generation of mobile LPSDR/LPDDR1 SDRAM and customer support - Professional supervision of layout, and physical verification Show less



ZMOS Technology, llc

• Seoul, Korea

• Senior Design Engineer

  • Apr 2004 - Sep 2007

  - Timing, function and power simulation, layout supervision and failure analysis - Definition and design of power domain control block to reduce leakage current - Calculation of optimal power gate size, location, speed degradation, and power dip analysis - Reduced layout time by development of in-house schematic-driven-layout tool - In-house design flow setup, toolkit development, and design automation - Improved design quality and increased vector coverage with logic simulation for LPSDR/LPDDR1 - Taped out 64Mb LPSDR1 SDRAM (130nm, 1.8V, 166MHz) - Taped out 128Mb LPDDR1 SDRAM (110nm, 1.8V/2.5V, 166MHz) - Taped out 512Mb LPDDR1 SDRAM (Hynix Joint Development, 90nm, 1.8V/2.5V, 200MHz) Show less



Silicon7

• Seoul, Korea

• Senior Design Engineer

  • Apr 2000 - Jan 2004

  - Timing, function and power simulation, layout supervision, failure analysis and customer support - Invented externally refresh-free operation scheme of DRAM and several US patents - Physical verification and timing simulation of pseudo-SRAM - Taped out 4, 8Mb pseudo-SRAM (UMC 0.21um, Tacc=70ns, 3.0V) and production - Taped out 16Mb pseudo-SRAM (NTC 0.175um, Tacc=70ns, 3.0V) and production - Taped out 16Mb pseudo-SRAM (NTC 0.145um, Tacc=70ns, 2.5V/3.0V) and production - Involved in Mega-order SRAM compiler development for Dongbu-Hitek Show less



SK hynix

• South Korea
• Semiconductor Manufacturing
• 700 & Above Employee

• Design Engineer

  • Oct 1995 - Feb 2000

  - Logic synthesis, optimization, simulation, place and route of hard macro blocks and full chips - Design of ALU datapath in 16/32bit CPU, multiplier, ROM, 1P/2P SRAM - synthesis, schematic capture, timing and function simulation, place and route, layout optimization, physical verification, parasitic RC extraction, post-simulation and model generation - Standard Cell Library development for datapath, cell spice timing simulation, layout, physical verification, parasitic RC extraction and modeling - SRAM tiling environment development Show less