Experience

Axelera AI

• Netherlands
• Semiconductor Manufacturing
• 1 - 100 Employee

• CPU SoC Engineer

  • Nov 2021 - Present



OpenHW Group

• Canada
• Semiconductor Manufacturing
• 1 - 100 Employee

• Director of Engineering, HW & SW Task Groups

  • Jun 2020 - Present

  As an HW & SW task group director, I am responsible for working closely and technically consulting member companies towards a unified vision, both from the HW (SoC definition, simulation, and verification) and the SW (compiler, HAL, SDK) side.OpenHW Group is a not-for-profit, global organization driven by its members (60+) and individual contributors where hardware and software designers collaborate to develop open-source cores, related IP, tools, and software. As an HW & SW task group director, I am responsible for working closely and technically consulting member companies towards a unified vision, both from the HW (SoC definition, simulation, and verification) and the SW (compiler, HAL, SDK) side.OpenHW Group is a not-for-profit, global organization driven by its members (60+) and individual contributors where hardware and software designers collaborate to develop open-source cores, related IP, tools, and software.



ETH Zürich

• Switzerland
• Higher Education
• 700 & Above Employee

• Postdoctoral Researcher

  • Mar 2021 - Oct 2021

  I currently lead the Occamy Project, an AI-focused realization of the Manticore many-core chiplet system I have presented at HotChips 2020. The system integrates two CVA6 CPUs with 576 Snitch cores as an accelerator on a dual-chiplet system on a passive SI interposer with private HBM2e and a high-bandwidth D2D interconnect based on Intel’s AIB standard.I am leading a small team of Ph.D. candidates. The project holistically spans from RTL design, physical design, FPGA emulation, U-Boot/Linux bring-up to application and compiler development.

• PhD Student

  • Sep 2017 - Mar 2021

  A PhD at ETH Zurich comes with a full-time scientific staff position. During my PhD, I was able to gather extensive experience in logic design (SystemVerilog), verification (UVM), physical design tools (Synopsys and Cadence products), as well as low-level programming (firmware, Linux kernel, embedded C/Rust).• I've designed, manufactured, and tested 9 ASICs in 22nm and 65nm technology nodes.• Designed and implemented a 64-bit RISC-V application-class core in multiple 22nm chips.• Analyzing the impact of the architecture and technology on energy efficiency, including multi-core scaling in a cache coherent many-core framework.• Authored and formally verified a RISC-V core and doubled its peak performance by allowing integer and float pipelines to operate in parallel in a pseudo-dual-issue mode.• Speaker at HotChips 2020, RISC-V Summit 2020, OSD Forum 2020, RISC-V Summit 2018, HPCA2018, RISC-V Workshop 2016.

• Student Assistent

  • Jun 2016 - Sep 2017

  I have been selected as a teaching assistant for the VLSI I-III courses.



Google

• United States
• Software Development
• 700 & Above Employee

• Hardware Engineer Intern

  • Jun 2018 - Sep 2018

  I (summer) interned at the Chip Implementation and Infrastructure group (CI2) at Google in Sunnyvale (CA). I (summer) interned at the Chip Implementation and Infrastructure group (CI2) at Google in Sunnyvale (CA).