Reda Razouk

Vice President, Process Technology at Altera
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Contact Information
us****@****om
(386) 825-5501
Location
San Jose, California, United States, US

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Experience

    • United States
    • Semiconductors
    • 700 & Above Employee
    • Vice President, Process Technology
      • Oct 2009 - Present

    • Semiconductor Manufacturing
    • 400 - 500 Employee
    • Vice President, World Wide Process Technology Development
      • Jan 2001 - Sep 2009

      Responsible for managing process technology development teams tasked with the development and deployment of all proprietary processes used by National Semiconductor product lines. Responsibility covers all aspects of process design, characterization, modeling and deployment of the technology at the company’s manufacturing sites in South Portland Maine, Arlington Texas and Glasgow Scotland. Technologies developed include Advanced CMOS and BiCMOS processes for digital logic, Analog Mixed Signal and Power products.

    • Director, Analog Process Technology Development
      • Jan 1991 - Dec 2000

      Responsible for the development of Analog proprietary processes used by National Semiconductor product lines. Responsibility covered all aspects of process design, characterization and deployment of the technology at the company’s manufacturing sites in Santa Clara, Salt Lake City and Glasgow Scotland. Technologies developed included Power BiCMOS/DMOS, Bipolar and High speed BiCMOS processes for Analog, Mixed Signal and Power technologies

    • Netherlands
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Manager
      • May 1987 - Dec 1990

      Manager of a Device Research group, a design support group and later an advanced MOS development group with a team in Sunnyvale and one in Albuquerque New Mexico. Responsibilities included exploratory processes and devices, development of sub-micron technologies for high density memories, and BiCMOS technologies aimed at high speed digital applications including micro-controllers with embedded memory, gate arrays and VLSI logic. Additional responsibilities included device characterization, model parameter extraction, and support for and technology-design trade-offs

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Manager
      • Jun 1978 - May 1987

      Held Several positions at Fairchild including• Manager, BiCMOS Development• Manager, MOS VLSI Research• Sr. Member of Research Staff Device Technology and VLSI Process Integration• Member of Research Staff, Device Technology Held Several positions at Fairchild including• Manager, BiCMOS Development• Manager, MOS VLSI Research• Sr. Member of Research Staff Device Technology and VLSI Process Integration• Member of Research Staff, Device Technology

Education

  • Purdue University
    BS, MS, Ph D, Electrical Engineering
    1968 - 1977

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