Experience

Semtech

• United States
• Technology, Information and Internet
• 700 & Above Employee

• ASIC Physical Design Staff Engineer

  • Apr 2022 - Present

• ASIC Physical Design Engineer

  • Mar 2019 - Mar 2022

  IP analysis and evaluation - Ensured potential new IP met performance targets and satisfied existing design requirements.IP integration - Took the lead in full front to back integration of IP within existing design flow. Working with IP provider for fast identification and diagnosis of issues.Physical design at chip top - Evaluating die size and aspect ratio options. I/O pad selection and padframe design.Top level chip finishing - Responsible for ensuring final GDS is ready for fabrication. Resolving chip top LVS/DRC/ERC issues in time sensitive situations.

• ASIC Physical Design Associate Engineer

  • May 2017 - Mar 2019

  - Silicon proven experience with independently taking a design through a full RTL to GDS flow. Carrying out activities such as Synthesis, DFT, Place and Route, STA, Physical & Formal Verification. - Analysis of Digital Designs using various performance metrics and providing recommendations towards critical design decisions. - Liaising with external EDA and Foundry Engineers to diagnose and resolve issues between design tools and Process Development Kits.- Floorplanning, Power Insertion, Placement Optimization, Clock Tree Synthesis, Routing and ECO using Synopsys IC Compiler & Cadence Encounter (Innovus).- Flow enhancement and development with a variety of Synopsys design tools (Design Compiler, Primetime, ICC, Formality & Lynx).- Utilizing EDA tools in a Unix environment, working with shell scripts and TCL. - Proficient with System Verilog for RTL.



Gennum Corporation (acquired by Semtech)

• Semiconductor Manufacturing
• 1 - 100 Employee

• Analog Design Engineering Intern

  • May 2015 - Aug 2016

  Projects3 Gb/s Receiver in TSMC 65nm CMOS- Used Cadence Virtuoso to construct organized test benches that were easy to follow for design team members.- Assisted the design team in carrying out top level verifications using circuit simulators like Cadence Spectre, Analog Fast Spice (AFS) and Analog Mixed-Signal (AMS.)- Documented verification results and ensured they were accurate and up to date. 3 Gb/s Transmitter in TSMC 65nm CMOS - Responsible for the design of several sub-blocks; ensured that they met and exceeded performance targets by performing various types of simulation (Schematic, Extracted, Monte-Carlo & EMIR).- Responsible for physical design (layout) of several designs using Virtuoso Layout Editor. - Ensured layouts were LVS and DRC clean using industry standard tools such as Assura and Calibre mmLVS/DRC.- Wrote behavioral models of simple analog circuits using Verilog-AMS and Verilog. - Assisted the digital team in ensuring certain Analog Circuits met timing requirements. - Assisted senior analog designers with verification tasks.- Worked with the design team to successfully carry out top level verification to ensure the project was tape-out ready.- Documented and conducted Design and Layout Reviews.28 Gb/s Optical Transceiver in 300 GHz FT BiCMOS- Responsible for the design and layout of CMOS bias circuitry.- Introductory exposure to floor planning of analog circuits, ensured physical designs addressed issues like matching, area and loading. - Assisted senior designers with managing design hierarchy ensuring that any changes were implemented promptly and that designs continued to work together coherently. - Responsible for training Analog Design Intern.