Kranthi Kella

Trained in RTL Design and Verification from Vlsi First.

Sushma Hiremath

|| Student || Design & Verification Engineer ||

Malathi Kanukula

Design verification Engineer || UVM ||SYSTEM-VERILOG || VERILOG

Deepak Ratnala

RTL Design and Verification Trainee at VLSI FIRST | Ex-Infoscion :- System Engineer @Infosys

Divya Kadiveti

Intern in VLSI FIRST

M B Bhanu Teja

Trained as Design verification Engineer and Physical design Engineer

Karri Manikanta Reddy

VLSI Enthusiast