Ivan Shevchuk

FPGA Design Engineer at Quantstellation
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Contact Information
us****@****om
(386) 825-5501
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Experience

  • Quantstellation
    • Capital Markets
    • 1 - 100 Employee
    • FPGA Design Engineer
      • Jul 2017 - Present
  • Asterismen GmbH
    • Germany
    • Software Development
    • FPGA Design Engineer
      • May 2016 - Jun 2017

      Berlin Area, Germany

  • НТЦ Метротек (STC Metrotek)
    • FPGA Design Engineer
      • Aug 2011 - Mar 2016

      Saint Petersburg, Russian Federation I was responsible for the FPGA firmware development for Ethernet packet processing (1G, 10G, 100G). These firmwares are used in ethernet test devices. Projects/Devices: - Bercut-ET/Bercut-ETX (Y.1564 / bugfixes / porting to new platforms) - Bercut-MX (various filters / TWAMP sender and reflector) - Metrotek B100 analyzer (RFC2544 / BERT) - Metrotek B100 balancer (various filters / load balancing)

Education

  • Saint Petersburg University of Telecommunications
    Specialist, Network Security
    2008 - 2013

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